The present invention relates generally to integrated circuit (IC) chips, and more particularly, to improved antifuse structures and methods for depositing antifuse layers to prevent deprogramming failures.
Fuse and antifuse structures have been used for sometime in certain classes of IC chips such as field programmable gate arrays, programmable read-only memories (PROMs) and the like. Field programmable gate arrays include a large number of logic elements, such as AND gates and OR gates, which can be selectively coupled together by means of fuses or antifuses to perform user designed functions. An unprogrammed fuse-type gate array is programmed by selectively blowing fuses within the device, while an unprogrammed antifuse type gate array is programmed by causing selected antifuses to become conductive.
There are many types of PROMs including standard, write-once PROMs, erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), etc. A PROM usually comprises an array of memory cells arranged in rows and columns, which can be programmed to store user data.
Fuses for field programmable gate arrays, PROMs and the like are typically made from a titanium-tungsten (TiW) alloy and are shaped somewhat like a bow-tie having a narrow, central neck and wide ends. The neck of the fuse is typically about 2 microns wide, while the ends of the fuse are typically about 6 microns wide. When a sufficiently high voltage (usually on the order of 10 volts D.C.) is applied to the fuse, the current flowing through the fuse will cause it to heat-up and will eventually melt the fuse at its neck, thereby "blowing" the fuse. Fuses in electronic devices are much more prevalent today than antifuses because they are easier to manufacture and have a better record of reliability.
Antifuses, however, do have the very desirable feature of being small in size. For example, a TiW fuse with a 2 micron neck and 6 micron end width permits approximately 4,000 fuses to be provided on a typical device. In contrast, a 1 or 1.2 micron diameter antifuse via permits 80,000-100,000 antifuses to be formed on a single device. As a result, antifuses provide designers with the ability to form larger numbers of antifuses for storing information on a typical devices than fuse technology storage.
Antifuse structures include a material which initially has a high resistance but which can be converted into a low resistance material by the application of a programming voltage. Once programmed, these low resistance antifuse structures can couple together logic elements of a field programmable gate array so that the gate array will perform user-desired functions, or can serve as memory cells of a PROM.
To facilitate further discussion, FIG. 1 schematically illustrates a cross section of a prior art antifuse structure 10. Antifuse structure 10 includes a "metal-one" layer 14, which is typically formed over an oxide layer of a semiconductor substrate, e.g., the silicon dioxide layer of a silicon wafer. Metal-one layer 14 typically comprises titanium-tungsten and/or other suitable conductive materials and may be formed by a conventional physical vapor deposition (PVD) process, such as sputtering.
Once metal-one layer 14 is formed, an antifuse layer 16 is blanket deposited and patterned using a suitable photolithographic process. Antifuse layer 16 is formed from amorphous silicon (a-Si), which has an intrinsic resistivity of approximately one mega-ohm-cm, and which may be deposited by any number of conventional processes, including chemical vapor deposition (CVD).
Following the amorphous silicon deposition, a barrier layer 17 is blanket deposited over antifuse layer 16. By way of example, barrier layer 17 may be a titanium-tungsten (TiW) layer configured to prevent aluminum atoms of subsequently deposited metallization layers from diffusing into and degrading antifuse layer 16. Next, an intermetal oxide (IMO) layer 18, typically consisting of silicon dioxide, is deposited above barrier layer 17 using any well-known process. A via hole 20 is then etched, using a suitable photolithographic process and an appropriate etchant. The via hole 20 therefore extends through inter-metal oxide layer 18 and stops at about barrier layer 17. A "metal-two" layer 22 then fills via hole 20 to create a metal contact to barrier layer 17 through inter-metal oxide layer 18.
The antifuse structure of FIG. 1 can then be programmed by applying an appropriate programming voltage between metal-one layer 14 and metal-two layer 22. For a typical amorphous silicon-based antifuse, the programming voltage is, for example, between about 8-12 volts D.C. at about 10 milli-amps (mA). During the programming step, antifuse layer 16 will typically form a conductive filament 24. Conductive filament 24 is generally formed when conductive atoms from metal-one layer 14 and/or conductive barrier layer 17 migrate into antifuse layer 16. A description of conducting filaments in programmed antifuse devices is found in a paper entitled "Conducting Filament of the Programmed Metal Electrode Amorphous Silicon Antifuse," Gordon et al., IEDM Tech. Dig., p. 27, December 1993, incorporated herein by reference.
A typical amorphous silicon-based antifuse structure 10 typically having a resistance of about 1-2 giga-ohms before programming (e.g., for a one micron diameter antifuse structure). After being programmed, the same antifuse structure 10 may have a resistance of about 20 to 100 ohms.
A problem often encountered with conventional antifuses is known as "deprogramming" (also referred to as infant mortality failures), in which antifuses having been subjected to a programming voltage are later found to have reverted to an unprogrammed "off" state. In some cases, deprogramming is a result of weakly "programmed" antifuse which initially forms an inadequate conductive filament. By way of example, antifuses with inadequate filament formation typically increase in resistance over time and essentially become unprogrammed as opposed to remaining in a low resistive state. Deprogramming problems may also result in programmed IC chip failures or latent defects that could potentially result in exceedingly expensive unsuspected future malfunctions.
In view of the forgoing, what is needed is a method for manufacturing amorphous silicon antifuse structures that maintain their programmed status thereby preventing infant mortality failures.